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FPGA Verification and Design Engineers

Innovate Recruitment Ltd
Posted 3 days ago, valid for 16 days
Location

Birmingham, West Midlands B4 6FQ

Salary

£45,000 - £65,000 per annum

Contract type

Full Time

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Sonic Summary

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  • The FPGA Verification and Design Engineers position is located in Birmingham, focusing on the design, verification, and implementation of advanced digital systems.
  • Candidates should have a minimum of 3 years of relevant experience and a strong background in digital design using VHDL and SystemVerilog.
  • The role offers a competitive salary of £50,000 to £70,000, along with an impressive benefits package including bonuses and employee support.
  • Responsibilities include developing complex digital ASIC/FPGAs, creating testbenches in SystemVerilog, and troubleshooting design and verification issues.
  • The company promotes a supportive and innovative environment, providing opportunities for growth and hybrid working options.

FPGA Verification and Design Engineers

Location: Birmingham

In this role, you’ll work as part of a dedicated team focused on the design, verification, and implementation of advanced digital systems for future projects.

These projects include developing innovative RISC-V processor cores, SoC ASICs, and sophisticated FPGA-based controllers.

An opportunity to be provided with outstanding growth opportunities, a competitive salary, and an impressive benefits package, including bonuses, employee support, and discounts.

If you’re ready to contribute to groundbreaking projects in a supportive and innovative environment, we’d love to hear from you!

Responsibilities

  • Developing complex digital ASIC/FPGAs using VHDL
  • Developing complex testbenches in SystemVerilog and UVM test environments.
  • Develop timely and effective solutions for problematic design & verification problems
  • Integrating debugging designs and supporting teams to resolve issues.

Who we’re looking for:

  • Detailed knowledge of digital design and appropriate languages, flows and methodologies.
  • Prior demonstrable experience using implementation tools, such as Simulators, synthesis engines, STA tools etc.
  • Strong prior experience of independently developing complex testbenches in SystemVerilog and UVM test environments.

For a design-oriented position,

  • Experience in VHDL and/or SystemVerilog RTL, with a proven track record of delivering high-volume deployed products.
  • Knowledge of the complete ASIC/FPGA design process, including synthesis, layout, and timing analysis, is essential.

For a verification-focused role,

  • strong proficiency in SystemVerilog and UVM, with a history of successful verification project completions.
  • Experience of writing, managing, and maintaining complex documentation and plans.
  • Experience in scripting with languages such as TCL, Python, Shell scripts
  • Experience in version control, such as Git, SVN.


Benefits

  • Hybrid Working
  • 25 days holiday + buy or sell optiona
  • Overtime ( double pay or additional holiday)
  • Annual bonus
  • Casual dress

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