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Are you an IC DFT Engineer who's passionate about cutting-edge technology and looking for a new opportunity to join a fantastic Cambridge based business, working in a collaborative environment?
This multi-disciplinary engineering company who have world-leading expertise and are offering innovative solutions around next generation technology.
You'll play a crucial role in overseeing and co-ordinating all aspects of integrated circuit (IC) design for test (DFT) activities.
You'll be an excellent communicator with good organisational skills, who can proactively support colleagues and spot areas for improvement.
Responsibilities include:
Design For Testability (DFT) - ATPG / MBIST
- Responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing
- DFT mode timing Analysis and sign off
- Responsible for a comprehensive DFT plan and drive the implementation
- Working with cross functional teams
- Train and mentor other test engineers
- Work with extended teams to develop project schedules and execute projects to completion
- Generating, verifying and debugging HDL and firmware-based test cases for DFT features of Flash-based FPGA
- Improving, extending, and porting existing DFT circuits and concepts to FPGA
- Developing test-benches and documenting test plans
- Create and maintain comprehensive DFT documentation, requirements specifications, and test plans
Technical Expertise
- Possess in-depth knowledge of analog and digital IC design principles
- Experience of scan-stitching; and has good knowledge of scan-stitching related concepts.
- Experience of MBIST/BISR implementation.
- Has worked on ATPG and is well conversed with the files required to run ATPG.
- Knowledge / experience with various EDA tools like Tessent ATPG (mentor) is a plus
- Has worked on Spyglass-Lint.
- Knowledgeable on TestMAX ATPG and TestMAX DFT
- Knowledgeable on test automation scripts
- Knowledgeable on JTAG, I2C, I3C
- Experience of supporting Spyglass debug and coverage co-relation
- Knowledgeable in debugging DRC and other scan-related issues
- Experience of supporting ATPG and debug ATPG issues
- Experience of supporting MBIST/BISR insertion and debug insertion or verification issues
- Experience of supporting gate-level simulations
Essential Skills
- Strong IC design and verification skills and relevant knowledge
- Knowledge of EDA tools like, Tessent, Cadence Module or TestMax
- Analytical thinking and attention to detail
- Proficiency in using computer software and relevant tools
- Highly skilled individual with many successful tape outs/experience
- MBIST expert
- ATPG / scan insertion expert
- Scan compression, JTAG, OCC
- Function test generation
- Very good vector generation and simulation skills
- Experienced at interacting with external OSAT / test engineers
- Industry knowledge of ATE test systems like Teradyne or Advantest
Qualifications
- An undergraduate degree or higher in engineering, physics, or a similar subject.
Location:
Cambridge (Hybrid working possible)
Hours:
Monday-Friday - Full-time
Salary:
Excellent salary on offer
Benefits:
25 days annual leave, Private Health Insurance, Life Insurance, regular social/team events, travel opportunities and more.
EA First Ltd are acting as an Employment Agency for this permanent vacancy.
