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Description:
We are reimagining high-performance computing by leveraging intelligent adaptive algorithms to accelerate supercomputers and drive them into the next generation. Our software-defined hardware architecture enables HPC to achieve groundbreaking advances across various research fields.
We are looking for a talented, motivated, and fast-learning Design Verification Engineer to help develop cutting-edge CPU technology for the HPC world. This is a unique opportunity to define, build, and drive verification environments from scratch, making a real impact within a dynamic and forward-thinking team.
Requirements:
3+ years of verification experience, including hands-on experience
3+ building complex verification environments from scratch
Expertise in verification languages such as SystemVerilog, UVM, OVM, and Specman Knowledge of industry-standard tools like Verilog, Verilog simulators, and debugging techniques Strong understanding of constrained random verification, functional coverage, code coverage, and assertion methodologies Advanced knowledge of verification flow, CPU, and SoC architecture and design (preferred) Experience with protocols like PCIe, CXL, CHI, HBM, and DDR (preferred) Familiarity with Perl, Tcl, shell scripting, and Makefiles (preferred) Master's degree in Electrical Engineering, Computer Science, or equivalent experience
Responsibilities:
Build and maintain a scalable verification environment that integrates with various systems (SW stack, FPGA, and ASIC RTL) Collaborate with software, design, and micro-architecture teams to understand functional and performance goals Review specifications and develop attributes, tests, and coverage plans Define verification methodology and design test benches Work closely with the verification team to ensure product quality
