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Location: Manchester
Working Environment: Hybrid (2days/week on-site)
The company is one of the most prestigious tech firms in the world and a global powerhouse in the semiconductor industry, operating at the bleeding edge of technology and redefining the way we interact with our devices through the creation of advanced semiconductor and software designs.
You will be joining theirSystems IPteam as an experienced Formal Verification engineer, reviewing and assessing proposed design changes and taking ownership of the verification environment from investigation through to verification closure. You will be developing, extending, maintaining and improving their SVA formal testbenches and suite of SVA protocol checkers for Formal and Simulation use. Furthermore, you will have the opportunity to improve their verification methodoly and mentor other members of the team.
Key Requirements:
- Experience of architecting and implementing formal verification environments for complex IP/module level designs.
- Experience of property-based model-checking or Formal Property verification.
- Practical experience of writing assertions using SystemVerilog Assertions (SVA) with an industry leading formal tool (e.g. Cadence, Mentor, Synopsys tools).
- Team leadership and mentoring experience
- Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI)
