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Design Verification Engineer

IC Resources
Posted a month ago, valid for 7 days
Location

Reading, Berkshire RG17LT, England

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • The Design Verification Engineer position in Berkshire offers an opportunity to work in an innovative technology environment.
  • The role involves developing high-performance, low-power signal processing solutions and requires ownership of digital verification for IC developments.
  • Candidates must have experience in verification planning, SystemVerilog, and testbench design with frameworks like UVM/OVM, along with debugging skills.
  • A competitive base salary is offered, along with a bonus scheme and stock options.
  • The position requires a minimum of 5 years of relevant experience and is hybrid, necessitating some in-office work.
Design Verification Engineer - Berkshire

This is an opportunity for a Design Verification Engineer to join an innovative environment and an organisation making changes in the technology sector.

The Design Verification Engineer will join a team developing high-performance, low-power signal processing solutions in audio, voice, and haptics, delivering innovative end-user experiences and solving difficult challenges for new generations of mobile and consumer devices.

You will join the team in Berkshire and will take ownership of all aspects of digital verification for complete IC developments, work on complex verification subsystems and will contribute towards improvements in methodology.

Responsibilities
  • Definition of IC verification plan linking product requirements through to detailed testcases
  • Leading teams of verification engineers to deliver thoroughly verified ICs
  • Create reliable and reusable testbench for complex subsystems and ICs
  • Participate in verification Specialist Groups and contribute to the digital verification methodology discussions
  • Hands-on project design/verification involvement
Required Skills and Qualifications
  • Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysis
  • SystemVerilog
  • Testbench design with verification frameworks like UVM/OVM, e, VMM
  • Debugging skills - RTL - Testbench, OOP - Gate level (including SDF)
  • Formal verification and verification qualification techniques
  • Scripting experience with Ruby, sh/csh, TCL, Make, Perl - advantage
This is a hybrid on-site position and will follow a 2+ day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance or be willing to relocate.

On offer is a competitive base salary, bonus scheme and stock options.

For more information please contact Rachel Mason at IC Resources

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In order to submit this application, a TotalJobs account will be created for you. As such, in addition to applying for this job, you will be signed up to all TotalJobs’ services as part of the process. By submitting this application, you agree to TotalJobs’ Terms and Conditions and acknowledge that your personal data will be transferred to TotalJobs and processed by them in accordance with their Privacy Policy.